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Protect The Parasitic Inductance In The Circuit

Aug 02, 2018

The parasitic inductors in the VS diode pathway produce severe overvoltage in the event of ESD events. Although TVS diode is used, the induction voltage at both ends of the inductive load is due VL=L * di/dt, high overshoot voltage may still exceed the damage voltage threshold of the protected IC.

The total voltage withstand by the protection circuit is the sum of TVS diode clamp voltage and parasitic inductance voltage, VT=VC+VL. An ESD transient induction current can be reached in less than 1ns to the peak (according to IEC 61000-4-2 standard), the lead inductance is assumed to be 20nH per inch, the line length is 1/4 inch, and the overshoot voltage will be 50V/10A pulse. Empirical design criteria, the shunt channel are designed to be as short as possible to reduce the parasitic inductance effect.

All inductive circuits must take into account the use of ground circuits, TVS and protected signal lines, and connections to TVS devices. The protected signal line shall be connected directly to the ground where it is connected. If no ground is connected, the connection of the ground loop shall be as short as possible. The distance between the grounding of TVS diode and the connection point of the protected circuit should be as short as possible to reduce the parasitic inductance of the ground plane.

Finally, TVS devices should be as close to the connector as possible to reduce transient coupling into nearby circuits. Although there is no direct access to the connector, this secondary radiation effect can also cause other parts of the circuit board to work out of order.


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